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19-2157; Rev 1; 10/02
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
General Description
The MAX1895/MAX1995 integrated controllers are optimized to drive cold-cathode fluorescent lamps (CCFL) using a synchronized full-bridge inverter architecture. Synchronized drive provides near sinusoidal waveforms over the entire input range to maximize the life of CCFLs. The controllers also operate over a wide input voltage range with high efficiency and broad dimming range. The MAX1895/MAX1995 include safety features that limit the transformer secondary voltage and protect against single-point fault conditions including lamp-out and short-circuit faults. The MAX1895/MAX1995 regulate the CCFL brightness in three ways: linearly controlling the lamp current, digital pulse-width modulating (DPWM) the lamp current, or using both methods simultaneously to achieve the widest dimming range (>30:1). CCFL brightness can be controlled with either an analog voltage (both MAX1895 and MAX1995) or a two-wire SMBusTM compatible interface (MAX1895 only). The MAX1895/MAX1995 directly drive the four external N-channel power MOSFETs of the full-bridge inverter. An internal 5.3V linear regulator powers the MOSFET drivers, the synchronizable DPWM oscillator, and most of the internal circuitry. The MAX1895/MAX1995 are available in the space-saving 28-pin thin QFN package and operate over the -40C to +85C temperature range.
Features
o Synchronized-to-Resonant Frequency Good Crest Factor for Longer Lamp Life Ensures Maximum Strike Capability o High Power to Light Efficiency o Wide Dimming Range (3 Methods) Lamp Current Adjust: >3 to 1 Digital PWM (DPWM): >10 to 1 Combined: >30 to 1 o Feed-Forward for Fast Response to Step Change of Input Voltage o Wide Input Voltage Range (4.6V to 28V) o Transformer Secondary Voltage Limiting to Reduce Transformer Stress o Lamp-Out Protection with 2s Timeout o Short-Circuit and Other Single-Point Fault Protections o Synchronizable DPWM Frequency o Dual-Mode Brightness Control Interface SMBus Serial Interface (MAX1895 Only) Analog Interface (Both Devices) o High-Accuracy Analog Interface Separate 100% Brightness Voltage Reference Pin (CRFSDA) Separate Minimum Lamp-Current Set-Point Pin (MINDAC) o Small Footprint 28-Pin Thin QFN (5mm x 5mm) Package
MAX1895/MAX1995
Applications
Notebook Computers Car Navigation Displays LCD Monitors Point-of-Sale Terminals Portable Display Electronics
Pin Configurations
N.C. CCI VFB IFB
BATT
28
27
26
CCV
VCC
TOP VIEW
25
24
23
Ordering Information
PART MAX1895ETI MAX1895EGI* MAX1995ETI MAX1995EGI* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 Thin QFN 5 5 28 QFN 5 5 28 Thin QFN 5 5 28 QFN 5 5
22
ILIM REF MINDAC GND MODE CRF/SDA CTL/SCL
1 2 3 4 5 6 7 10 11 12 13 14 8 9
21 20 19
GH2 LX2 BST2 BST1 LX1 GH1 GL1
MAX1895
18 17 16 15
*Contact factory for availability. Pin Configurations continued at end of data sheet. SMBus is a trademark of Intel Corp.
N.C.
N.C.
PGND
N.C.
SH/SUS
THIN QFN
________________________________________________________________ Maxim Integrated Products
GL2
VDD
1
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
ABSOLUTE MAXIMUM RATINGS
BATT to GND..........................................................-0.3V to +30V BST1, BST2 to GND ...............................................-0.3V to +36V BST1 to LX1, BST2 to LX2 ........................................-0.3V to +6V GH1 to LX1 ...............................................-0.3V to (BST1 + 0.3V) GH2 to LX2 ...............................................-0.3V to (BST2 + 0.3V) VCC, VDD to GND .....................................................-0.3V to +6V REF, ILIM to GND .......................................-0.3V to (VCC + 0.3V) GL1, GL2 to GND .......................................-0.3V to (VDD + 0.3V) MINDAC, IFB, CCV, CCI to GND .............................-0.3V to +6V MODE to GND ...........................................................-6V to +12V VFB to GND..................................................................-6V to +6V CRF/SDA, CTL/SCL, SH/SUS to GND ......................-0.3V to +6V PGND to GND .......................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 28-Pin QFN (derate 20.84mW/C above +70C) .......1667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VBATT = 12V, MINDAC = GND, VCC = VDD, V SH/SUS = 5.3V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note1)
PARAMETER VBATT Input Voltage Range VBATT Quiescent Current VBATT Quiescent Current, Shutdown VCC Output Voltage, Normal Operation VCC Output Voltage, Shutdown VCC Undervoltage Lockout Threshold VCC Undervoltage Lockout Hysteresis VCC POR Threshold VCC POR Hysteresis REF Output Voltage, Normal Operation GH1, GH2, GL1, GL2 On-Resistance GH1, GH2, GL1, GL2 Maximum Output Current BST1, BST2 Leakage Current Input Resonant Frequency Minimum Off-Time Maximum Off-Time Maximum Current-Limit Threshold LX1-GND, LX2-GND (Fixed) Maximum Current-Limit Threshold LX1-GND, LX2-GND (Adjustable) ILIM = VCC VILIM = 0.5V VILIM = 2.0V BST_ = 12V, LX_ = 7V Guaranteed by design 20 200 20 180 80 370 300 30 200 100 400 Rising edge Falling edge 4.5V < VCC < 5.5V, ILOAD = 40A ITEST = 100mA, VCC = VDD = 5.3V 1.96 0.9 CONDITIONS VCC = VDD = VBATT VCC = VDD = open V SH /SUS = 5.5V SH /SUS = 0 V SH /SUS = 5.5V, 6V < VBATT < 28V 0 < ILOAD < 20mA SH /SUS = GND, no load VCC rising (leaving lockout) VCC falling (entering lockout) 4 200 1.75 50 2.00 2 1 5 300 400 40 220 120 430 2.04 6 2.7 5.0 3.5 VBATT = 28V VBATT = VCC = 5V 6 5.35 4.6 MIN 4.6 5.5 3.2 TYP MAX 5.5 28 6 6 20 5.5 5.5 4.5 UNITS V mA A V V V mV V mV V A A kHz ns s mV mV
2
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VBATT = 12V, MINDAC = GND, VCC = VDD, V SH/SUS = 5.3V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note1)
PARAMETER Minimum Current-Crossing Threshold LX1-GND, LX2-GND Current-Limit Leading-Edge Blanking D/A Converter Resolution MINDAC Input Voltage Range MINDAC Input Bias Current MINDAC Digital PWM Disable Threshold IFB Input Voltage Range VMINDAC = 0, DAC code = 11111 binary IFB Regulation Point IFB Input Bias Current IFB Lamp-Out Threshold IFB to CCI Transconductance CCI Output Impedance VFB Input Voltage Range VFB Input Bias Current VFB Regulation Point VFB to CCV Transconductance VFB Zero-Voltage Crossing Threshold CCV Output Impedance No AC signal on MODE Digital PWM Chop-Mode Frequency MODE to DPWM Sync Ratio Lamp-Out Detection Timeout Timer (Note 2) MODE Operating Voltage Range MODE Input Current Positive Analog Interface Mode MODE = GND Threshold (VCTL/SCL = 0 sets minimum brightness) Negative Analog Interface Mode MODE = REF Threshold (VCTL/SCL = 0 sets maximum brightness = 0) SMBus Interface Mode MODE = VCC Threshold MODE = GND or VCC Sync clock average value on MODE to sync DPWM oscillator, not in shutdown. (Note 3) 32kHz AC signal on MODE 100kHz AC signal on MODE fMODE/fDPWM NO AC signal on MODE VIFB < 0.1V 32kHz AC signal on MODE 100kHz AC signal on MODE -5.5 -1 2.10 205 1V < VCCV < 2.7V -10 20 220 250 781 128 2.33 2.05 0.66 +11.0 +1 0.6 V A V 2.60 s 235 Hz VFB = 0 -2 -0.5 490 510 40 +10 1V < VCCI < 2.5V VMINDAC = 0, DAC code = 00100 binary VMINDAC = 1V, DAC code = 00000 binary MINDAC = VCC Guaranteed monotonic 200 5 0 -2 2.4 0 368 30 180 -2 125 150 100 20 +2 0.5 530 388 50 200 3.5 2 +2 4.0 1.7 408 70 220 +2 175 A mV S M V A mV S mV M mV CONDITIONS MIN TYP 6 300 400 MAX UNITS mV ns Bits V A V V
MAX1895/MAX1995
Sync clock average value on MODE to sync DPWM oscillator, not in shutdown. (Note 3) Sync clock average value on MODE to sync DPWM oscillator, not in shutdown. (Note 3)
1.4 VCC 0.6
2.6
V
V
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3
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
ELECTRICAL CHARACTERISTICS (continued)
(VBATT = 12V, MINDAC = GND, VCC = VDD, V SH/SUS = 5.3V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note1)
PARAMETER MODE AC Signal Amplitude MODE AC Signal Synchronization Range CRF/SDA Input Range CRF/SDA Input Current CTL/SCL Input Range CTL/SCL Input Current A/D Converter Resolution A/D Converter Hysteresis SH /SUS Input Low Voltage SH /SUS Input High Voltage SH /SUS Input Hysteresis SH /SUS Input Bias Current SDA, SCL Input Low Voltage SDA, SCL Input High Voltage SDA, SCL Input Hysteresis SDA Output Low Sink Current SCL Serial Clock High Period SCL Serial Clock Low Period Start Condition Setup-Time Start Condition Hold-Time SDA Valid to SCL Rising-Edge Setup Time, Slave Clocking in Data SCL Falling-Edge to SDA Transition SCL Falling-Edge to SDA Valid, Reading Out Data VCRF/SDA = 0.4V THIGH TLOW tSU:STA tHD:STA tSU:DAT tHD:DAT TDV 4 4 4.7 4.7 4 250 0 700 2.1 300 2.1 300 -1 +1 0.8 MODE = REF or GND Guaranteed monotonic VCRF/SDA = 5.5V, SH /SUS = VCC VCRF/SDA = 5.5V, SH /SUS = 0 -1 0 -1 5 1 0.8 CONDITIONS Peak-to-peak (Note 4) Chopping oscillator synchronized to MODE MIN 2 32 2.7 TYP MAX 5 100 5.5 20 +1 VCRF/SDA +1 UNITS V kHz V A V A bits LSB V V mV A V V mV mA s s s s ns ns ns
ELECTRICAL CHARACTERISTICS
(VBATT = 12V, MINDAC = GND, VCC = VDD, V SH/SUS = 5.3V, TA = -40C to +85C, unless otherwise noted.) (Note1)
PARAMETER VBATT Input Voltage Range VBATT Quiescent Current VBATT Quiescent Current, Shutdown CONDITIONS VCC = VDD = VBATT VCC = VDD = open V SH/SUS = 5.5V V SH/SUS = 0 VBATT = 28V VBATT = VCC = 5V MIN 4.6 5.5 TYP MAX 5.5 28.0 6 6 20 UNITS V mA A
4
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VBATT = 12V, MINDAC = GND, VCC = VDD, V SH/SUS = 5.3V, TA = -40C to +85C, unless otherwise noted.) (Note1)
PARAMETER VCC Output Voltage, Normal Operation VCC Output Voltage, Shutdown VCC Undervoltage Lockout Threshold VCC POR Threshold REF Output Voltage, Normal Operation GH1, GH2, GL1, GL2 On-Resistance Maximum Current-Limit Threshold LX1-GND, LX2-GND (Fixed) Maximum Current-Limit Threshold LX1-GND, LX2-GND (Adjustable) IFB Input Voltage Range IFB Regulation Point IFB Input Bias Current IFB Lamp-Out Threshold VFB Input Voltage Range VFB Input Bias Current VFB Regulation Point VFB Zero-Voltage Crossing Threshold SHVSUS Input Low Voltage SHVSUS Input High Voltage SDA, SCL Input Low Voltage SDA, SCL Input High Voltage SDA Output Low Sink Current VCRF/SDA = 0.4V 2.1 4 2.1 0.8 VFB = 0 VMINDAC = 0, DAC code = 11111 binary CONDITIONS V SH/SUS = 5.5V, 6V < VBATT < 28V 0 < ILOAD < 20mA SH/SUS = GND, no load VCC rising (leaving lockout) VCC rising (entering lockout) Rising edge 4.5V < VCC < 5.5V, ILOAD = 40A ITEST = 100mA ILIM = VCC VILIM = 0.5V VILIM = 2.0V 180 80 360 0 335 -1 120 -2 -0.1 480 -20 4.0 0.9 1.96 2.7 2.04 10 220 120 440 1.7 440 +1 180 +2 +0.1 540 +20 0.8 MIN 5.0 3.5 TYP MAX 5.5 5.5 4.5 UNITS V V V V V mV mV V mV A mV V A mV mV V V V V mA
MAX1895/MAX1995
Note 1: Specifications to -40C are guaranteed by design based on final test characterization results. Note 2: Corresponds to 512 DPWM cycles or 65536 MODE cycles. Note 3: The MODE pin thresholds are only valid while the part is operating. When in shutdown VREF = 0 and the part only differentiates between SMB mode and ADC mode. When in shutdown and with ADC mode selected the CRF/SDA and CTL/SCL pins are at high impedance and will not cause extra supply current when their voltages are not at GND or VCC. Note 4: The amplitude is measured with the following circuit:
VAMPLITUDE > 2V 500pF MODE 10k
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Typical Operating Characteristics
(VBATT = 12V, VCTL = VCRF, VMINDAC = 1V, MODE = GND, circuit of Figure 1, Table 4.)
LOW INPUT VOLTAGE OPERATION (VBATT = 8V) HIGH INPUT VOLTAGE OPERATION (VBATT = 20V)
VFB 2V/div IFB 2V/div LX1 10V/div
FEED-FORWARD COMPENSATION
MAX1895 toc03
MAX1895 toc01
MAX1895 toc02
VFB 2V/div IFB 2V/div LX1 10V/div
20V VBATT 10V VFB 2V/div IFB 2V/div LX1 10V/div 20s/div
LX2 10V/div
LX2 10V/div
10s/div
10s/div
STARTUP
MAX1895 toc04
SYNCHRONIZED DPWM (fMODE = 100kHz, DPWM = 50%)
12V VBATT 0V VFB 2V/div IFB 2V/div IBATT 500mA/div
MAX1895 toc05
SYNCHRONIZED DPWM (fMODE = 32kHz, DPWM = 50%)
IFB 1V/div VFB 1V/div LX1 10V/div LX2 10V/div
MAX1895 toc06
IFB 1V/div VFB 1V/div LX1 10V/div LX2 10V/div 1ms/div
1ms/div
1ms/div
LAMP-OUT VOLTAGE LIMITING
MAX1895 toc07
LAMP-OUT PROTECTION
MAX1895 toc08
VCC vs. VBATT
NORMAL OPERATION VSECONDARY 2kV/div VCC (V) 5 4 3 2 1 0 0 5 10 15 20 25 VBATT (V) SHUTDOWN
MAX1895 toc09
6
2s VSECONDARY 2kV/div
VFB 2V/div
VFB 2V/div
LAMP REMOVED 2ms/div
IFB 1V/div
LAMP REMOVED 400ms/div
IFB 1V/div
6
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Typical Operating Characteristics (continued)
(VBATT = 12V, VCTL = VCRF, VMINDAC = 1V, MODE = GND, circuit of Figure 1, Table 4.)
VCC LOAD REGULATION
5.40 NORMAL OPERATION 5.35 SHUTDOWN 5.30 VCC (V) 5.25 5.20 5.15 5.10 0.01 0.1 1 ILOAD (mA) 10
VCC vs. TEMPERATURE
4.6 4.5 4.4 4.3 4.2 4.1 4.0 100 SHUTDOWN VCC (V) 5.36 SHUTDOWN 5.35
MAX1895 toc10
MAX1895 toc11
4.60
4.55 SHUTDOWN VCC (V)
VCC (V)
5.34 NORMAL OPERATION 5.33
4.50
4.45
5.32
4.40
5.31 -40 -15 10 35 60 85 TEMPERATURE (C)
4.35
Pin Description
PIN NAME FUNCTION Current-Limit Threshold Adjustment. Bias ILIM with a resistive voltage-divider between REF or VCC and GND. The current-limit threshold measured between LX_ and GND is 1/5th of the voltage at ILIM, ILIM adjustment range is 0 to 3V. Connect ILIM to VCC to set the default current-limit threshold to 0.2V. 2V Reference Output. Bypass REF to GND with a 0.1F capacitor. REF is discharged to GND when shutdown. DAC Zero-Scale Input. VMINDAC sets the D/A converter's minimum-scale output voltage. Disable DPWM by connecting MINDAC to VCC. System Ground. The GND input to the maximum and minimum current-limit comparators. The comparators sense the low-side FET NL1 and NL2 for zero-current crossing and current limit. Interface Selection Input and Sync Input for DPWM Chopping. The average voltage on the MODE pin selects one of three CCFL brightness control interfaces: MODE = VCC enables SMBus serial interface. MODE = GND enables the analog interface (positive analog interface mode), VCTL/SCL = 0 sets minimum brightness. MODE = REF enables the analog interface (reverse analog interface mode), VCTL/SCL = 0 sets maximum brightness. An AC clocking signal superimposed on the DC average MODE pin voltage can be used to synchronize the DPWM chopping frequency. See Synchronizing the DPWM Frequency. Reference and Serial Data Input. In analog interface mode, pin 6 is the reference input to the 5-bit brightness control ADC. Bypass CRF to GND with a 0.1F capacitor. In SMBus Interface mode (MAX1895 only), SDA is an SMBus serial data input/open-drain output.
1
ILIM
2 3 4
REF MINDAC GND
5
MODE
6
CRF/SDA
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7
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Pin Description (continued)
PIN 7 NAME CTL/SCL FUNCTION Brightness Control and Serial Clock Input. In analog interface mode, pin 7 is a CCFL brightness control input. CTL varies from 0V to REF to linearly control lamp brightness. In SMBus Interface mode (MAX1895 only), SCL is an SMBus serial clock input. Shutdown and Suspend Mode Control. In analog interface mode, pin 8 is an active-low shutdown input. In SMBus interface mode (MAX1895 only), pin 8 is an SMBus suspend control input. No Connection. Not internally connected. Power Supply for Gate Drivers. Connect VDD to the output of the linear regulator (VCC). Bypass VDD with a 0.1F capacitor to PGND. Power Ground. Gate-driver current flows through this pin. Low-Side FET NL2 Gate-Driver Output Low-Side FET NL1 Gate-Driver Output High-Side FET NH1 Gate-Driver Output Switching Node Connection. LX1 is the internal lower supply rail for the GH1 high-side gate driver. LX1 is also the sense input to the current comparators. High-Side FET NH1 Driver Bootstrap Input. Connect BST1 through a diode to VDD and through a 0.1F capacitor to LX1. (See Figure 1.) High-Side FET NH2 Driver Bootstrap Input. Connect BST2 through a diode to VDD and through a 0.1F capacitor to LX2. (See Figure 1.) Switching Node Connection. LX2 is the internal lower supply rail for the GH2 high-side gate driver. LX2 is also the sense input to the current comparators. High-Side FET NH2 Gate-Driver Output Lamp-Output Feedback-Sense Input. The average value on VFB is regulated during startup and open-lamp conditions to 0.5V by controlling the on time of high-side switches. A capacitive voltagedivider between the CCFL lamp output and GND is sensed to set the maximum average lamp output voltage. Lamp Current-Sense Input. The voltage on IFB is used to regulate the lamp current. If the IFB input falls below 150mV for 2 seconds, then the MAX1895/MAX1995 signals an open-lamp fault. Current-Loop Compensation Pin. CCI is the output of the current-loop transconductance amplifier (GMI) that regulates the CCFL current. The CCI voltage controls the time interval in which fullbridge applies the input voltage (BATT) to transformer network. Connect CCI to GND through a 0.1F capacitor. CCI is internally discharged to GND in shutdown. Voltage-Loop Compensation Pin. CCV is the output of the voltage-loop transconductance amplifier (GMV) that regulates the maximum average secondary transformer voltage. Load CCV to GND with a 10nF capacitor. The pin voltage controls the time interval that the full bridge applies the input voltage (BATT) to transformer network. CCV is internally discharged to GND in shutdown. Supply Input. Input to the internal 5.3V linear regulator that provides power (VCC) to the chip. Bypass BATT to GND with a 0.1F capacitor. 5.3V Linear-Regulator Output. VCC is the supply voltage for the MAX1895. Bypass VCC to GND with a 0.47F ceramic capacitor. VCC can also be connected to BATT if VBATT < 5.5V.
8 9, 10, 11, 23 12 13 14 15 16 17 18 19 20 21
SH/SUS N.C. VDD PGND GL2 GL1 GH1 LX1 BST1 BST2 LX2 GH2
22
VFB
24
IFB
25
CCI
26
CCV
27 28
BATT VCC
8
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
VIN 5V TO 28V C1 NH1 NH2 C2 T1 C3 NL1 NL2 C4 R2 CCFL R1 D1
GH1
GH2
GL1
LX1 C5 BST1 D2-1
PGND
BATT
GL2
LX2 C6
BST2 D2-2
VCC
C7 GND C8
VDD
MAX1895
CCV
MINDAC
VFB IFB
SH/SUS
R3 ON/OFF R4 C10 REFERENCE INPUT CONTROL INPUT
Figure 1. Standard Application Circuit
Detailed Description
The MAX1895/MAX1995 are optimized to drive coldcathode fluorescent lamps (CCFL) using a synchronized full-bridge inverter architecture. The drive to the full-bridge MOSFETs is synchronized to the resonant frequency of the tank circuit so that the CCFL's fullstrike voltage develops for all operating conditions. The synchronized architecture provides near sinusoidal drive waveforms over the entire input range to maximize the life of CCFLs. The MAX1895/MAX1995 operate over a wide input voltage range (4.6V to 28V), achieve high efficiency, and maximize dimming range. The MAX1895/MAX1995 regulate the brightness of a CCFL in 3 ways:
REF
CCI
MODE
C9
CRF/SDA
CTL/SCL
ILIM
1) Linearly controlling the lamp current. 2) Digitally pulse-width modulating (or chopping) the lamp current (DPWM). 3) Using both methods simultaneously for widest dimming range. DPWM is implemented by pulse-width modulating the lamp current at a rate faster than the eye can detect. The MAX1895/MAX1995 include a 5.3V linear regulator to power the drivers for full-bridge switches, the synchronizable DPWM oscillator, and most of the internal circuitry. The MAX1895 is very flexible and can be controlled with an analog interface or with an SMBus interface. The MAX1995 only supports analog interface.
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9
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
VBATT VBATT
NH1 ON T1 C2 LX1 LX2
NH2 OFF
NH1 OFF T1 C2 LX1 LX2
NH2 ON
NL1 OFF
NL2 ON
NL1 ON
NL2 OFF
(a) VBATT
(c) VBATT
NH1 OFF T1 C2 LX1 LX2
NH2 OFF
NH1 OFF T1 C2 LX1 LX2
NH2 OFF
NL1 ON (BODY DIODE TURNS ON FIRST) (b)
NL2 ON
NL1 ON
NL2 ON (BODY DIODE TURNS ON FIRST) (d)
Figure 2. Resonant Operation
Resonant Operation
The MAX1895/MAX1995 drive the four N-channel power MOSFETs that make up the zero-voltage switching (ZVS) full-bridge inverter as shown in Figure 1. The LX1 and LX2 switching nodes are AC coupled to the primary side of the transformer. Assume that NH1 and NL2 are turned on at the beginning of the cycle as shown in Figure 2(a). The primary current flows through MOSFET NH1, DC blocking cap C2, the primary side of transformer T1, and finally MOSFET NL2. During this interval, the primary current ramps up until the controller turns off NH1. When NH1 is off, the primary current forward biases the body diode of NL1 and brings the LX1 node down as shown in Figure 2(b). When the controller turns on NL1, its drain-tosource voltage is near zero because its forward-biased body diode clamps the drain. Since NL2 is still on, the primary current flows through NL1, C2, the primary side of T1, and finally NL2. Once the primary current drops
10
to the minimum current threshold (6mV/RDSON), the controller turns off NL2. The remaining energy in T1 charges up the LX2 node until the body diode of NH2 is forward biased. When NH2 turns on, it does so with near zero drain-to-source voltage. The primary current reverses polarity as shown in Figure 2(c), beginning a new cycle with the current flowing in the opposite direction, with NH2 and NL1 on. The primary current ramps up until the controller turns off NH2. When NH2 is off, the primary current forward biases the body diode of NL2, and brings the LX2 node down as shown in Figure 2(d). After the LX2 node goes low, the controller losslessly turns on NL2. Once the primary current drops to the minimum current threshold, the controller turns off NL1. The remaining energy charges up the LX1 node until the body diode of NH1 is forward biased. Finally, NH1 losslessly turns on, beginning a new cycle as shown in Figure 2(a).
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
CS 1:N
AC SOURCE
CP
CS/(NxN)
LI
AC SOURCE
CP
RB
Figure 3. Equivalent Circuit
Note that switching transitions on all four power MOSFETs occur under ZVS conditions, which reduces transient power losses and EMI. The equivalent circuit of the resonant tank is shown in Figure 3. The resonant frequency is determined by the RLC resonant tank elements: CS, CP, LL, and RB. CS is the series capacitance on the primary side of the transformer. CP is the parallel cap on the transformer's secondary. L L is the transformer secondary leakage inductance. RB is an idealized resistance which models the CCFL load in normal operation.
either the SMBus interface (MAX1895 only) or the analog interface (both MAX1895 and MAX1995) (see Dimming Range section). This error voltage is called VCCI. In normal operation, the current loop is in control of the regulator so long as VCCI is less than VCCV. The control signal is compared with an internal ramp signal to set the high-side switch on time (tON). When DPWM is employed, the two control loops work together to limit the transformer voltage and to allow wide dimming range with good line rejection. During the DPWM off-cycle, VCCV is set to 1.2V and the currentloop error amplifier output is high impedance. VVFB is set to 0.6V to create a soft-start at the beginning of each DPWM on-cycle in order to avoid overshoot on the transformer's secondary. When the transconductance amplifier in the current loop is high impedance, it acts like a sample-and-hold circuit, to keep VCCI from changing during the off-cycles. This action allows the current control loop to regulate the average lamp current. See the Current Sense Resistor and the Voltage Sense Capacitors sections for information regarding setting the current- and voltage-loop thresholds.
MAX1895/MAX1995
CCFL
Startup
Operation during startup differs from the steady-state condition described in the current and voltage loop section. Upon power-up, VCCI slowly rises, increasing the duty cycle, which provides soft-start. During this time, VCCV, which is the faster control loop, is limited to 150mV above VCCI. Once the secondary voltage reaches the strike voltage, the lamp current begins to increase. When the lamp current reaches the regulation point, VCCI exceeds VCCV and it reaches steady state. With MINDAC = VCC, DPWM is disabled and the current loop remains in control regulating the lamp current.
Current and Voltage Control Loops
The MAX1895/MAX1995 use a current loop and a voltage loop to control the energy applied to the CCFL. The current loop is the dominant control in setting the lamp brightness. The rectified lamp current is measured with a sense resistor in series with the CCFL. The voltage across this resistor is applied to the IFB input to regulate the average lamp current. The voltage loop controls the voltage across the lamp and is active during the beginning of DPWM on-cycles and the open-lamp fault condition. It limits the energy applied to the resonant network once the transformer secondary voltage is above the threshold of 500mV average measured at VFB. Both voltage and current circuits use transconductance-error amplifiers to compensate the loops. The voltage-error amplifier creates an error current based upon the voltage difference between VFB and the internal reference level (typically 500mV) (Figure 4). The error current is then used to charge and discharge a capacitor at the CCV output (CCCV) to create an error voltage CCCV. The current loop produces a similar signal at CCI based on the voltage difference between IFB and the dimming control signal. This signal is set by
Feed-Forward Control
The MAX1895/MAX1995 have a feed-forward control circuit, which influences both control loops. Feed-forward control instantly adjusts the tON time to changes in input voltage. This feature provides immunity to changes in input voltage at all brightness levels and makes compensation over wide input ranges easier. The feed-forward circuit improves line regulation for short DPWM on times and makes startup transients less dependent on input voltage. Feed-forward control is implemented by varying the internal voltage ramp rate. This has the effect of varying tON as a function of input voltage while maintaining about the same signal levels at VCCI and VCCV. Since the required voltage change across the compensation capacitors is minimal, the controller's response to change in VBATT is essentially instantaneous.
11
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
REFERENCE INPUT CRF/SDA LAMP CURRENT AND DPWM CONTROL CTL/SCL SMBus CONTROL INPUT MODE DPWM OSC VCC DPWM COMP BATT MINDAC
SUPPLY
REF
SH/SUS MINDAC = VCC Y = 1, N =0 0.15V CCV BST1 0.5V GMV VFB CCI CCV CLAMP RAMP GENERATOR GMI IFB PK_DET CLAMP 4mV LX2 LX1 MUX VDD REF ILMIT IMAX COMP GL2 PGND PEAK DETECTOR IMIN COMP LX2 CCFL LX1 CONTROL LOGIC PWM COMP GH1
GND
BST2
GH2
GL1
GND
MAX1895 MAX1995
Figure 4. Functional Diagram
Transient Overvoltage Protection from Dropout
The MAX1895/MAX1995 are designed to maintain tight control of the transformer secondary under all transient conditions including dropout. To maximize run time, it is desirable to allow the circuit to operate in dropout at extremely low battery voltages where the backlight's performance is not critical. When VBATT is very low, the controller can lose regulation and run at maximum duty cycle. Under these circumstances, a transient overvoltage condition could occur when the AC adapter is suddenly applied to power the circuit. But the feed-forward circuitry minimizes variations in lamp voltage due to such input voltage steps. The regulator also clamps the voltage on VCCI. Both features ensure that overvoltage
transients do not appear on the transformer when leaving dropout. The VCCI clamp is unique in that it limits at the peaks of the voltage-ramp generator. As the circuit reaches dropout, VCCI approaches the peaks of the ramp generator in order to reach maximum t ON . If V BATT decreases further, the control loop loses regulation and VCCI tries to reach its positive supply rail. The clamp on VCCI prevents this from happening and VCCI rides just above the peaks of the PWM ramp. If VBATT continues to decrease, the feed-forward PWM ramp generator loses amplitude and the clamp drags VCCI down with it to a voltage below where VCCI would have been if the circuit were not in dropout. When VBATT suddenly steps out of dropout, VCCI is still low and maintains the drive on the transformer at the old dropout level. The control
12
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Table 1. Interface Modes
DIGITAL INTERFACE (MAX1895 ONLY) PIN MODE = VCC SH/SUS CRF/SDA CTL/SCL SMBus suspend SMBus data I/O SMBus clock input MODE = REF VCTL/SCL = 0 = maximum brightness Logic level shutdown control input Reference input for minimum brightness Reference input for maximum Analog control input to set brightness (range from 0 to CRF/SDA) MODE = GND VCTL/SCL = 0 = minimum brightness ANALOG INTERFACE
loop then slowly corrects and increases VCCI to bring the circuit back into regulation.
Interface Selection
Table 1 describes the functionality of SH/SUS, CRF/ SDA, and CTL/SCL in each of the MAX1895's three interface modes. The MAX1895 features both an SMBus Digital Interface and an Analog Interface. Note that the MODE signal can also synchronize the DPWM frequency. (See Synchronizing the DPWM Frequency.)
If VIFB does not exceed 150mV peak (which is about 47.7mV/R1 RMS lamp current) for greater than 2s, the MAX1895/MAX1995 assumes a lamp-out condition and shuts down (see Lamp-Out Detection section). The equation relating brightness code to IFB regulation voltage is: VIFB = VREF n/160 + VMINDAC (32 - n)/160 where n is the brightness code. To always use maximum average lamp current when using DPWM control, set VMINDAC to VREF. DPWM control works similarly to lamp-current control as it also responds to the 5-bit brightness code. A brightness code of 00000\b corresponds to a 9% DPWM duty cycle and a brightness code of 11111\b corresponds to a 100% DPWM duty cycle. The duty cycle changes by 3.125% per step, but codes 00000\b to 00011\b all produce 9% (Figure 5). To disable DPWM and always use 100% duty cycle, set VMINDAC to VCC. Note that with DPWM disabled, the equations shown above should assume VMINDAC = 0 instead of VMINDAC = VCC. Table 2 describes MINDAC's functionality and Table 3 shows some typical settings for the brightness adjustment. In normal operation, VMINDAC is set between 0 and VREF and the MAX1895/MAX1995 use both lamp-current control and DPWM control to vary the lamp brightness. In this mode, lamp-current control regulates the average lamp current during a DPWM on-cycle.
Dimming Range
The brightness is controlled by either the Analog Interface (for both MAX1895 and MAX1995, see Analog Interface section) or the SMBus Interface (for MAX1895 only, see SMBus Interface section). The brightness of the CCFL is adjusted in the following three ways: 1) Lamp-current control, where the magnitude of the average lamp current is adjusted. 2) DPWM control, where the average lamp current is pulsed to the set level with a variable duty cycle. 3) The combination of the first two methods. In each of the three methods, a 5-bit brightness code is generated from the selected interface and is used to set the lamp current and/or DPWM duty cycle. The 5-bit brightness code defines the lamp current level with 00000\b representing minimum lamp current and 11111\b representing maximum lamp current. The average lamp current is measured across an external sense resistor (see Current-Sense Resistor section). The voltage on the sense resistor is measured at IFB. The brightness code adjusts the regulation voltage at IFB (VIFB). The minimum average VIFB is VMINDAC/5 (VMINDAC = 0~2V) and the maximum average is set by the following formula: VIFB = VREF 31/160 +VMINDAC /160 which is between 387.5mV and 400mV.
Analog Interface and Brightness Code
The MAX1895/MAX1995's analog interface uses an internal ADC with 1-bit hysteresis to generate the brightness code used to dim the lamp (see Dimming Range section). CTL/SCL is the ADC's input and CRF/SDA is its reference voltage. The ADC can operate in either positive-scale ADC mode or negative-scale ADC mode. In positive-scale ADC mode, the brightness code increases from 0 to 31 as VCTL increases from 0 to VCRF. In
13
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
DPWM SETTINGS
100 90 80 DPWM DUTY CYCLE (%) 70 60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 32 BRIGHTNESS CODE COMBINED POWER LEVEL (%)
COMBINED POWER LEVEL (BOTH DPWM AND LAMP-CONTROL CURRENT)
100 90 80 70 60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 32 BRIGHTNESS CODE
Figure 5. DPWM Settings
Figure 6. Combined Power Level
Table 2. MINDAC Functionality
CONDITION MINDAC = VCC MINDAC = REF 0 VMINDAC < VREF FUNCTION DPWM disabled (always on 100% duty cycle). Operates in lamp-current control only. (Use VMINDAC = 0 in the equations.) DPWM control enabled, duty cycle ranges from 9% to 100%. Lamp-current control is disabled (always maximum current). The device uses both lamp-current control and DPWM.
Table 3. Brightness Adjustment Ranges
RANGE POSITIVE-SCALE ADC MODE MODE = GND VCRF/SDA = VCTL/SCL MODE = GND VCRF/SDA = 0 VMINDAC = 1/3VREF NEGATIVE-SCALE ADC MODE SMBus DAC OUTPUT Full-scale DAC output = 387.5mV Zero-scale DAC output = VMINDAC / 5 DPWM DUTY CYCLE COMBINED POWER LEVEL
Maximum Brightness
MODE = REF VCRF/SDA = 0 MODE = REF VCRF/SDA = VCTL/SCL VMINDAC = 1/3VREF
Bright [4:0] = 11111
100%
100%
Minimum Brightness
Bright [4:0] = 00000 VMINDAC = 1/3VREF
9%
3%
Note: The current level range is solely determined by the MINDAC to REF ratio and is externally set.
negative-scale mode, the brightness scale decreases from 31 to 0 as VCTL increases from 0 to VCRF. The analog interface's internal ADC uses 1-bit hysteresis to keep the lamp from flickering between two codes.
14
V CTL 's positive threshold (V CTL(TH) ) is the voltage required to transition the brightness code as V CTL increases and can be calculated as follows:
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
VCTL(TH) = (n + 2)/33 VCRF (Positive-Scale ADC mode, MODE = GND) VCTL(TH) = (33 - n)/33 VCRF (Negative-Scale ADC mode, MODE = REF) VCTL's negative threshold is the voltage required to transition the brightness code as VCTL decreases and can be calculated as follows: VCTL(TH) = n/33 VCRF (Positive-Scale ADC mode, MODE = GND) VCTL(TH) = (31 - n)/33 VCRF (Negative-Scale ADC mode, MODE = REF) where n is the brightness code. See Figure 7 for a graphical representation of the thresholds. See the Digital Interface section for instructions on using the SMBus interface. Unlike conventional dimming control circuits that have separate supplies and require additional minimum brightness circuitry, the MAX1895/MAX1995 provide dedicated pins for dimming control. The advantages of
MAX1895/MAX1995 INTERFACE CONVENTIONAL INTERFACE
MAX1895/MAX1995
VCCA
VCCB
DIMMING CONTROL CIRCUIT
MIN. DIM CKT.
VCTL
INVERTER CONTROLLER
0 TO VMAX VCCA VCCB
VCRF DIMMING CONTROL CIRCUIT VCTL MINDAC MAX1895
REF
Figure 8. Analog Interface for Dimming
31 30 29
3 2 1 0 1 33 2 33 3 33 4 33 VCTL VCRF 30 33 31 33 32 33 1
the MAX1895/MAX1995's analog interface are illustrated in Figure 8. The analog interface is very simple in that the output voltage range of the dimming control circuit matches the input voltage range of the inverter control IC. With this method it is possible to guarantee the maximum dimming range (Figure 9). For the conventional interface, the control voltage and the input voltage have different ranges. To avoid nonuniform lighting across the CCFL tube, or the "thermometer effect", the lower limits of maximum and minimum control voltages have to be above the upper limits of the maximum and minimum input voltages, respectively. Therefore, the useful dimming range is reduced. For the MAX1895/MAX1995's analog interface, the control voltage has the same range as the input voltage, so the useful dimming range is maximized.
BRIGHTNESS CODE
Synchronizing the DPWM Frequency
MODE has two functions: one is to select the Interface mode as described in Interface Selection and the other is to synchronize the DPWM "chopping" frequency to an external signal to prevent unwanted artifacts in the display screen. To synchronize the DPWM frequency, connect MODE to VCC, REF, or GND through a 10k resistor. Then connect a 500pF capacitor from an AC signal source to MODE as shown in Figure 10. The amplitude of the AC signal must be at least 2V peak-to-peak but no greater than 5V peak-to-peak for accurate operation. The transition time of the AC signal should be less than 200s. The synchronization range is 32kHz to 100kHz, which
15
(MODE = GND)
1
32 33
31 33
30 33 VCTL VCRF
29 33
3 33 (MODE = REF)
2 33
1 33
0
Figure 7. Brightness Code
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
MAX. BRIGHTNESS CONTROL VOLTAGE
TOLERANCE MAX. BRIGHTNESS INPUT VOLTAGE TYPICAL DIMMING RANGE
CONVENTIONAL INTERFACE
MIN. BRIGHTNESS CONTROL VOLTAGE
TYPICAL DIMMING RANGE LOST MIN. BRIGHTNESS INPUT VOLTAGE GND
MAX. BRIGHTNESS CONTROL VOLTAGE
TOLERANCE
MAX. BRIGHTNESS INPUT VOLTAGE
MAX1895/MAX1995 INTERFACE
TYPICAL DIMMING RANGE
MIN. BRIGHTNESS CONTROL VOLTAGE
GND
MIN. BRIGHTNESS INPUT VOLTAGE
Figure 9. Useful Dimming Range
corresponds to a DPWM frequency range of 250Hz to 781Hz (128 MODE pulses per DPWM cycle). High DPWM frequencies limit the dimming range. See Loop Compensation for more information concerning high DPWM frequencies. A simple oscillator circuit as shown in Figure 11 can be used to generate the synchronization signal. The core of the oscillator is the MAX9031, which is a low-cost, single-supply comparator in a 5-pin SC70 package. The VCC and REF of the MAX1895/MAX1995 provide the supply voltage and the reference voltage for the
16
oscillator. The positive threshold of the oscillator is: VTH+ = (VCC + VREF)/2. The negative threshold is given by: VTH+ = VREF/2. The frequency of the oscillator is calculated as follows:
f= 1 VTH+ (VCC - VTH- ) RCln VTH- (VCC - VTH+ )
For C = 330pF, a 13k resistor generates a 100kHz signal and a 39k resistor generates a 32kHz signal.
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
VL REF ADC10k MODE SMBus ADC+ 500pF GND DPWM SYNCHRONIZATION SIGNAL C R MAX1895 MAX1995
MAX9031
REF 100k 1%
100k 1%
VCC
TO MODE
Figure 10. DPWM Synchronization
Figure 11. A Simple RC Oscillator
POR and UVLO
The MAX1895/MAX1995 include power-on reset (POR) and undervoltage lockout (UVLO) circuits. The POR resets all internal registers such as DAC output, fault conditions, and all SMBus registers. POR occurs when VCC is below 1.5V. The SMBus input-logic thresholds are only guaranteed to meet electrical characteristic limits for VCC as low as 3.5V, but the interface will continue to function down to the POR threshold. The UVLO is activated and disables both high-side and low-side switch drivers when VCC is below 4.2V (typ).
voltage control loop is able to quickly limit the secondary voltage. Without this clamping feature, the transformer voltage would overshoot to dangerous levels because VCCV would take more time to slew down from its supply rail. If the peak voltage on IFB does not rise above 150mV before timeout, the MAX1895/MAX1995 shut down the full bridge.
Overcurrent Fault Detection and Protection
The MAX1895/MAX1995 sense overcurrent faults on each switching cycle. The current comparator monitors the voltage drop from LX_ to GND. If the voltage exceeds the current-limit threshold, the regulator turns off the high-side switch to prevent the transformer primary current from increasing further.
Low-Power Shutdown
When the MAX1895/MAX1995 are placed in shutdown, all functions of the IC are turned off except for the 5.3V linear regulator that powers all internal registers and the SMBus interface (MAX1895 only). The SMBus interface is accessible in shutdown. In shutdown, the linear regulator output voltage drops to about 4.5V and the supply current is 6A (typ), which is the required power to maintain all internal register states. While in shutdown, lamp-out detection and short-circuit detection latches are reset. The device can be placed into shutdown by either writing to the shutdown mode register (MAX1895 SMBus mode only) or with SH/SUS.
Applications Information
The MAX1895's standard application circuit, shown in Figure 1, regulates the current of a 4.5W CCFL. The IC's analog voltage interface sets the lamp brightness with a greater than 30 to 1 power adjustment range. This circuit operates from a wide supply voltage range of 4.6V to 28V. Typical applications for this circuit include notebook, desktop monitor, and car navigation displays. Table 4 shows the recommended components for the power stage of the 4.5W application. To select the correct component values, several CCFL parameters (Table 6) and the DC input characteristics must be specified.
Lamp-Out Detection
For safety, the MAX1895/MAX1995 monitor the lamp current to detect the open-lamp fault. When the peak voltage on IFB drops below 150mV (IFB regulation point must be set above 48mV) the lamp-out timer starts. Before the timer times out, VCCI increases the secondary voltage in an attempt to maintain lamp-current regulation. As VCCI rises, VCCV rises with it until the secondary voltage reaches its preset limit. At this point, VCCV stops and limits the secondary voltage by limiting tON. Because VCCV is limited to 150mV above VCCI the
MOSFETs
The MAX1895/MAX1995 require four external switches NL1, NL2, NH1, and NH2 to form a full bridge to drive CCFL. The regulator senses drain-to-source voltage of NL1 and NL2 to detect the transformer primary minimum current crossing and overcurrent fault condition.
17
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Table 4. Components for the Standard Application Circuit
DESIGNATION DESCRIPTION RECOMMENDED DEVICE TMK325BJ475MN C1 4.7F, 25V, X5R ceramic capacitor C3225X7R1E475M MANUFACTURER Taiyo Yuden www.t-yuden.com TDK www.tdk.com Taiyo Yuden TDK Murata www.murata.com TDK Taiyo Yuden Murata Taiyo Yuden Murata TDK Panasonic www.panasonic.com Fairchild Semiconductor www.fairchildsemi.com General Semiconductor www.gensemi.com Central Semiconductor www.centralsemi.com Diodes Incorporates www.diodes.com Central Semiconductor Fairchild Semiconductor Toshiba www.toshiba.com
C2
1F, 25V, X7R ceramic capacitor
TMK316BJ105KL C3216X7R1E105K GHM1038-SL-150J-3K C4520C0G3F150K EMK105BJ153KV GRM36X7R153K016 LMK105BJ104MV GRM36X5R104K010 C10055R1A104K ECJ-0EB1C103K MMBD4148SE
C3
15pF, 3.1kV, high-voltage ceramic capacitor
C4 C5, C6, C7, C8, C10 C9
0.015F, 16V, X7R ceramic capacitor
0.1F,10V, X5R ceramic capacitors
0.01F, 16V, X7R ceramic capacitor
D1
100mA dual-series diode
MMBD7000 CMPD7000
D2
100mA dual Schottky diode common anode
BAT54AW CMSSH-3A FDC6561AN
NH1/NL1, NH2/NL2 R1 R2 R3 R4 T1
Dual N-channel MOSFETs (30V, 0.095, SOT23-6) 150 1% resistor 2k 5% resistor 100k 1% resistor 49.9k 1% resistor 1:100 transformer
TPC6201
T912MG-1018
Toko www.tokoam.com
RDSON of NL1 and NL2 should be matched. Select a dual logic-level N-channel MOSFET with low RDSON to minimize conduction loss for NL1/NL2 and NH1/NH2 (Fairchild FDC6561). The regulator softly turns on each of four switches in the full bridge. ZVS (zero-voltage switching) occurs when the external power MOSFETs
18
are turned on while their respective drain-to-source voltages are near zero volts. ZVS effectively eliminates the MOSFET transition losses caused by CRSS (drainto-source capacitance) and parasitic capacitance discharge. ZVS improves efficiency and reduces switching-related EMI.
______________________________________________________________________________________
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
Current-Sense Resistor
The MAX1895/MAX1995 regulate the CCFL average current through the sense resistor R1 in Figure 1. The voltage at IFB is the half-wave rectified representation of the current through the lamp. The inverter regulates the average voltage at IFB, which is controlled by either the analog interface or the SMBus interface. To set the maximum lamp RMS current, determine R1 as follows: R1 = 0.444V/ICCFL, RMS, MAX, where ICCFL, RMS, MAX is the maximum RMS lamp current. MINDAC and the wave shape influence the actual maximum RMS lamp current. If necessary, use an RMS current meter to make final adjustments to R1. 50kHz (Fmin) and 200kHz (Fmax). The transformer T1, the DC blocking capacitor C2, the parallel capacitor C3, and the CCFL lamp form a resonant tank. The resonant frequency is determined by the transformer secondary leakage inductance L, C2, and C3. The tank is a bandpass filter whose lower frequency is bounded by L, N, and C2. N is the transformer's turns ratio. Choose C2 N 2 (10 F 2 MIN L). The upper frequency is bounded by L and C3. Choose C3 1/(40 F2MIN L).
MAX1895/MAX1995
Other Components
The high-side MOSFET drivers (GH1 and GH2) are powered by the external bootstrap circuit formed by D2, C5 and C6. Connect BST1/BST2 through a dual signal-level Schottky diode D2 to VDD, and connect it to LX1/LX2 with 0.1F ceramic capacitors. Use a dualseries signal-level diode (D1) to generate the half-wave rectified current-sense voltage across R1. The current through these diodes is the lamp current.
Voltage-Sense Capacitors
The MAX1895/MAX1995 limit the transformer secondary voltage during open-lamp fault through the capacitive divider C3/C4. The voltage of VFB is proportional to CCFL voltage. To set the maximum RMS secondary transformer voltage, choose C3 around 10pF to 22pF, and select C4 such that C4 = VT(MAX)/1.11V x C3, where VT(MAX) is the maximum RMS secondary transformer voltage (above the strike voltage). R2 sets the VFB DC bias point to 0V. Choose R2 =10/(C4 6.28 FSW), where FSW is the nominal resonant operating frequency.
Dual-Lamp Regulator
The MAX1895/MAX1995 can be used to drive two CCFL tubes as shown in Figure 12. See Table 5 for component selection. The circuit consists of two identical transformers with primary windings connected in parallel and secondary windings in series. The two transformers can also be replaced with a single transformer, which has one primary winding and two secondary windings. The advantage of the series secondary windings is that the same current flows through both lamps resulting in approximately the same brightness. In normal operation, C12 is charged to approximately 6V biasing N1 on, which permits current to flow in the loop as follows: in the first half-cycle, current flows through the secondary winding of T1, CCFL1, diode D1, MOSFET N1, sense resistor R1, Zener diode D4 (forward bias), CCFL2, finally returning to T2. In the second half-cycle the lamp current flows through T2, CCFL2, D4 (breakdown), D3 (forward bias), CCFL1, and back to T1. The roundabout path of current flow is necessary in order to detect an open-lamp condition when either CCFL is removed. If CCFL1 is open, the lamp current cannot flow through the sense resistor R1. When IFB drops below 150mV the controller detects the condition and shuts down after a 2s delay. During the delay current can flow from T2 through CCFL2, D4 (breakdown), and R6 back to T2. If CCFL2 is removed, the voltage across D4 drops to zero and C11 is discharged through R5. N1 is biased off which forces the voltage at IFB to drop to zero once again. During the 2s turn-off delay, current flows from T1 to CCFL1 through D3
19
Loop Compensation
CCI sets the speed of the current loop that is used during startup, maintaining lamp current regulation, and during transients caused by changing the lamp-current settling. The typical CCI capacitor value is 0.1F. Larger values limit lamp-current overshoot, but increase setting time. Smaller values speed up its response time, but extremely small values can lead to instability. CCV sets the speed of the voltage loop that affects startup, DPWM transients and operation in an opentube fault condition. If DPWM is not used, the voltage control loop should only be active during startup or an open-lamp fault. The CCV capacitor typical value is 0.01F. Use the smallest value of CCV capacitor necessary to set an acceptable fault-transient response and not cause excessive ringing at the beginning of a DPWM pulse. Larger CCV capacitor values reduce transient overshoot, but can degrade regulation at low DPWM duty cycles by increasing the delay to strike voltage.
Resonant Components
The MAX1895/MAX1995 work well with air-gap transformers with turns ratio N in the order of NP:NS = 1:90 to 1:100 for most applications. The transformer secondary resonant frequency must be controlled. A lowprofile CCFL transformer typically operates between
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
VIN 5V TO 28V C1 NH1 NH2 C2 T1 CCFL C3 NL1 NL2 D3 D6 D1 N1
R1
C4 R6
R2
R7
GH1
GH2
GL1
PGND
BATT
GL2
C11 LX2 C6 T2
R6
LX1 C5 BST1 D2-1
BST2 D2-2 C13
D4 D5 CCFL2
C12
R5
VCC
C7 GND C8
VDD
MAX1895
VFB IFB
CCV
MINDAC
SH/SUS
R3 ON/OFF R4 C10 REFERENCE INPUT CONTROL INPUT
Figure 12. Dual-Lamp Application Circuit
(breakdown) and R6 back to T1. D3 clamps the drain of N1 enabling the use of a MOSFET with modest breakdown characteristics. The secondary voltages of both transformers are monitored through the two identical capacitive voltage dividers (C3/C4 and C13/C11). The dual diode D6 rectifies the two sensed voltages and passes the signal to the VFB pin. A full-wave rectified sinusoidal waveform appears at the VFB pin. The RMS value of this new VFB signal is greater than the half-wave rectified signal in the single-lamp application. To compensate for the waveform change and the forward voltage drop in the diodes, the capacitive voltage-divider ratio must be decreased. Choose C3 around 10pF to 22pF, and select C4 according to C4 = VT, MAX /1.33V C3,
20
REF
CCI
MODE
C9
CRF/SDA
CTL/SCL
ILIM
where VT, MAX is the maximum transformer secondary RMS voltage.
Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The high voltage and switching power stages require particular attention (Figure 13). The high-voltage sections of the layout need to be well separated from the control circuit. Most layouts are constrained to long narrow PC boards, so this separation occurs naturally. Follow these guidelines for good PC board layout: 1) Keep the high-current paths short and wide, especially at the ground terminals. This is essential for stable, jitter-free operation, and high efficiency.
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
Table 5. Components for the Dual-Lamp Application Circuit
DESIGNATION DESCRIPTION RECOMMENDED DEVICE TMK325BJ475MN C1 4.7F, 25V, X5R ceramic capacitor C3225X7R1E475M TMK316BJ105KL C3216X7R1E105K GHM1038-SL-150J-3K C4520C0G3F150K EMK105BJ153KV GRM36X7R153K016 LMK105BJ104MV GRM36X5R104K010 C1005X5R1A104K ECJ-0EB1C103K MMBD4148 D1, D5 100mA diodes IMBD4148 MMBD4148 MANUFACTURER Taiyo Yuden www.t-yuden.com TDK www.tdk.com Taiyo Yuden TDK Murata www.murata. TDK Taiyo Yuden Murata Taiyo Yuden Murata TDK Panasonic www.panasonic.com Fairchild Semiconductor www.fairchildsemi.com General Semiconductor www.gensemi.com Diodes Incorporated www.diodes.com Diodes Incorporated Central Semiconductor www.centralsemi.com Central Semiconductor Diodes Incorporated Central Semiconductor Diodes Incorporated Fairchild Semiconductor General Semiconductor Central Semiconductor Fairchild Semiconductor Toshiba www.toshiba.com
MAX1895/MAX1995
C2
1F, 25V, X7R ceramic capacitor 15pF, 3.1kV, high-voltage ceramic capacitors 0.015F, 16V, X7R ceramic capacitors 0.1F, 10V, X5R ceramic capacitors
C3, C13
C4, C11 C5, C6, C7, C8, C10, C12 C9
0.01F, 16V, X7R ceramic capacitor
D2
100mA dual Schottky diode, common anode 6.2V zener diodes Dual diode, common cathode
BAT54AW CMSSH-3A CMPZ5234B BZX84C6V2 CMPD2838 BAV70 2N7002 2N7002 2N7002 FDC6561AN TPC6201
D3, D4 D6
N1
N-channel MOSFET (SOT23)
NH1/NL1, NH2/NL2 R1 R2, R6 R3 R4 R5 R7 T1, T2
Dual N-channel MOSFETs (30V, 0.095, SOT23-6) 150 1% resistor 2k 5% resistors 100k 1% resistor 49.9k 1% resistor 1k 5% resistor 20k 5% resistor 1:100 transformers
T912MG-1018
Toko www.tokoam.com
______________________________________________________________________________________
21
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
C4 C2 N1 N2 T1 C3 R2 LAMP D1
HIGH-CURRENT PRIMARY CONNECTION NOTE: DUAL MOSFET N2 IS MOUNTED ON THE BOTTOM SIDE OF THE PC BOARD DIRECTLY UNDER N1.
HIGH-VOLTAGE SECONDARY CONNECTION
Figure 13. Layout Example
Table 6. CCFL Specifications
SPECIFICATION CCFL Minimum Strike Voltage ("Kick-Off Voltage") SYMBOL UNITS DESCRIPTION Although CCFLs typically operate at <550VRMS, a higher voltage (up to 1000VRMS and beyond) is required initially to start the tube. The strike voltage is typically higher at cold temperatures and at the end of life of the tube. Once a CCFL has been struck, the voltage is required to maintain light output falls to approximately 550VRMS. Shorter tubes may operate on as little as 250VRMS. The operating voltage of the CCFL stays relatively constant, even as the tube's brightness is varied. The maximum AC current through a CCFL is typically 5mARMS. DC current is not allowed through CCFLs. The maximum lamp current is set by the sense resistor, R1, and the maximum brightness setting. R1 = 2.2 VIFBMAX/ILMAX. The maximum AC lamp-current frequency. The MAX1895/MAX1995 are designed to operate between 20kHz and 300kHz.
VS
VRMS
CCFL Typical Operating Voltage ("Lamp Voltage")
VL
VRMS
CCFL Maximum Operating Current ("Lamp Current") CCFL Maximum Frequency ("Lamp Frequency")
IL
mARMS
fL
kHz
2) Utilize a star ground configuration for power and analog grounds. The power ground and analog ground should be completely isolated--meeting only at the center of the star. The center should be placed at the backside contact to the QFN package. Using separate copper planes for these planes may simplify this task. Quiet analog ground is used for REF, CCV, CCI, RX, and MINDAC (if a resistive voltage-divider is used). 3) Route high-speed switching nodes away from sensitive analog areas (IFB, VFB, REF, ILIM). Make all pinstrap control input connections (ILIM, etc.) to analog ground or VCC rather than power ground or VDD. 4) Mount the decoupling capacitor from VCC to GND as close as possible to the IC with dedicated traces that are not shared with other signal paths.
5) The current sense paths for LX1 and LX2 to GND must be made using Kelvin sense connections to guarantee the current-limit accuracy. With SO-8 MOSFETs, this is best done by routing power to the MOSFETs from outside using the top copper layer, while connecting GND and LX inside (underneath) the SO-8 package. 6) Ensure the feedback connections are short and direct. To the extent possible, IFB and VFB connections should be far away from the high voltage traces and the transformer. 7) To the extent possible, high-voltage trace clearance on the transformer's secondary should be widely separated. The high voltage traces should also be separated from adjacent ground planes to prevent capacitive coupling losses.
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Write-Byte Format S ADDRESS 7 bits Slave Address WR 1b ACK 1b COMMAND 8 bits Command Byte: selects which register you are writing to ACK 1b DATA 8 bits ACK 1b P
Data Byte: data goes into the register set by the command byte
Read-Byte Format S ADDRESS 7 bits Slave Address WR 1b ACK 1b COMMAND 8 bits ACK 1b S ADDRESS 7 bits RD 1b ACK 1b DATA 8 bits /// 1b P
Command Byte: selects which register you are reading from
Slave Address: repeated due to change in dataflow direction Receive-Byte Format
Data Byte: reads from the register set by the command byte
Send-Byte Format S ADDRESS 7 bits WR 1b ACK 1b COMMAND 8 bits ACK 1b P
S
ADDRESS 7 bits Slave Address
RD 1b
ACK 1b
DATA 8 bits
/// 1b
P
Command Byte: sends command with no data; usually used for oneshot command S = Start condition P = Stop condition Shaded = Slave transmission Ack= Acknowledged = 0 /// = Not acknowledged = 1
WR = Write = 0 RD = Read =1
Data Byte: reads data from the register commanded by the last read-byte or write-byte transmission; also used for SMBus Alert Response return address
Figure 14. SMBus Protocols
8) The traces to the capacitive voltage-divider on the transformer's secondary need to be widely separated to prevent arcing. Moving these traces to opposite sides of the board can be beneficial in some cases (Figure 13).
Digital Interface
With MODE connected to V CC , the CRF/SDA and CTL/SCL pins no longer behave as analog inputs; instead they function as an Intel SMBus-compatible two-wire digital interface. CRF/SDA is the bidirectional data line and CTL/SCL is the clock line of the two-wire interface corresponding respectively to SMBDATA and SMBCLK lines of the SMBus. The MAX1895 uses the Write-Byte, Read-Byte, Send-Byte, and Receive-Byte protocols (Figure 14). The SMBus protocols are documented in "System Management Bus Specification v1.08" and are available at www.sbs-forum.org. The MAX1895 is a slave-only device and responds to the 7-bit address 0b0101101 (i.e., with the RW bit clear indicating a write, this corresponds to 0x5A). The MAX1895 has three functional registers: a 5-bit bright-
ness register (BRIGHT4-BRIGHT0), a 3-bit shutdown mode register (SHMD2-SHMDE0), and a 2-bit status register (STATUS1-STATUS0). In addition, the device has three identification (ID) registers: an 8-bit chip ID register, an 8-bit chip revision register, and an 8-bit manufacturer ID register. CRF/SDA and CTL/SCL pins have Schmidt-trigger inputs that can accommodate slow edges; however, the rising and falling edges should still be faster than 1s and 300ns, respectively. Communication starts with the master signaling the beginning of a transmission with a START condition, which is a high-to-low transition on CRF/SDA, while CTL/SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is low-to-high transition on CRF/SDA, while CTL/SCL is high. The bus is then free for another transmission. Figures 15 and 16 show the timing diagram for signals on the 2-wire interface. The address-byte, command-byte, and data-byte are transmitted between the START and STOP conditions. The CRF/SDA state is allowed to change only while
23
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
A tLOW B tHIGH C D E F G H I J K L M
SMBCLK
SMBDATA
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tHD:DAT
tSU:STO tBUF J = ACKNOWLEDGE CLOCKED INTO MASTER K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION, DATA EXECUTED BY SLAVE M = NEW START CONDITION
A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE I = SLAVE PULLS SMBDATA LINE LOW
Figure 15. SMBus Write Timing
A tLOW
B tHIGH
C
D
E
F
G
H
I
J
K
SMBCLK
SMBDATA
tSU:STA tHD:STA A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE
tSU:DAT
tHD:DAT E = SLAVE PULLS SMBDATA LINE LOW F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO MASTER H = LSB OF DATA CLOCKED INTO MASTER
tSU:DAT
tSU:STO
tBUF
I = ACKNOWLEDGE CLOCK PULSE J = STOP CONDITION K = NEW START CONDITION
Figure 16. SMBus Read Timing
CTL/SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit words and is sampled on the rising edge of CTL/SCL. Nine clock cycles are required to transfer each byte in or out of the MAX1895 since either the master or the slave acknowledges the receipt of the correct byte during the ninth clock. If the MAX1895 receives its correct slave address followed by RW = 0, it expects to receive one or two bytes of information (depending on the protocol). If the device detects a start or stop condition prior to clocking in the bytes of data, it considers this an error condition and disregards all of the data. If the transmission is completed correctly the registers are updated immediately after a STOP (or RESTART) condition. If the MAX1895 receives its correct slave address followed by RW = 1, it expects to clock out the register data selected by the previous command byte.
24
SMBus Commands
The MAX1895 registers are accessible through several different redundant commands (i.e., the command-byte in the read-byte and write-byte protocols), which can be used to read or write the brightness, SHMD, status, or ID registers. Table 6 summarizes the command-byte's register assignments as well as each register's power-on state. The MAX1895 also supports the receive-byte protocol for quicker data transfers. This protocol accesses the register configuration pointed to by the last command byte. Immediately after power-up, the data-byte returned by the receive-byte protocol is the contents of the brightness register, left justified (i.e. BRIGHT4 will be in the most significant bit position of the data byte) with the remaining bits containing a one, STATUS1, and
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Table 7. Command Byte Description
DATA REGISTER BIT ASSIGNMENT SMBus PROTOCOL Read and Write Byte Read and Write Byte Read Byte only Read Byte only Read and Write Byte Read Byte only Read Byte only COMMAND BYTE* 0x01 0b0XXX XX01 0x02 0b0XXX XX10 0x03 0b0XXX XX11 0x04 0b0XXX XX00 0x80 0b10XX XX0X 0xFE 0b11XX XXX0 0xFF 0b11XX XXX1 POR STATE 0x17 0xF9 0x96 0x00 0xBF 0x4D 0x96 BIT 7 (MSB) 0 BIT 6 0 BIT 5 0 1 ChipID5 0 BIT 4 BRIGHT4 (MSB) 1 ChipID4 1 BIT 3 BRIGHT3 1 ChipID3 0 BIT 2 BIT 1 BIT 0 (LSB) BRIGHT0 (LSB) SHMD0 ChipID0 0 ChipRev0 0 STATUS0 MfgID0 1 ChipID0 0
BRIGHT2 BRIGHT1 SHMD2 ChipID2 1 SHMD1 ChipID1 1
STATUS1 STATUS0 ChipID7 1 ChipID6 0
ChipRev7 ChipRev6 ChipRev5 ChipRev4 0 0 0 0 BRIGHT4 BRIGHT3 BRIGHT2 (MSB) MfgID7 0 ChipID7 1 MfgID6 1 ChipID6 0 MfgID5 0 ChipID5 0 BRIGHT1 MfgID4 0 ChipID4 1
ChipRev3 ChipRev2 ChipRev1 0 0 0 BRIGHT0 (LSB) MfgID3 1 ChipID3 0 1 MfgID2 1 ChipID2 1 STATUS1 MfgID1 0 ChipID1 1
Note: The hexadecimal command byte shown is recommended for maximum forward compatibility with future products. X = Don't Care
STATUS0. This will give the same result as using the read-word protocol with 0b10XXXXXX (0x80) command. Use caution with the shorter protocols in multimaster systems, since a second master could overwrite the command byte without informing the first master. During shutdown the serial interface remains fully functional.
Status Register [STATUS1-STATUS0] (POR = 0b11)
The status register returns information on fault conditions. If a lamp is not connected to the secondary of the transformer, the MAX1895 will detect that the lamp current has not exceeded the IFB detection threshold and after 2s will clear the STATUS1 bit (see Lamp-Out Detection section). The STATUS1 bit is latched; i.e. it will remain 0 even if the lamp-out condition goes away. When STATUS1 = 0, the lamp is forced off. STATUS0 reports `1' as long as no overcurrent conditions are detected. If an overcurrent condition is detected in any given digital PWM period, STATUS0 is cleared for the duration of the following digital PWM period. If an overcurrent condition is not detected in any given digital PWM period, STATUS0 is set for the duration of the following digital PWM period. Forcing the CCFL lamp off by entering shutdown, writing to the mode register, or by toggling SHB/SUS sets STATUS1.
Brightness Register [BRIGHT4-BRIGHT0] (POR = 0b10111)
The 5-bit brightness register corresponds with the 5-bit brightness code used in the dimming control (see Dimming Control). BRIGHT4-BRIGHT0 = 0b00000 sets minimum brightness and BRIGHT4-BRIGHT0 = 0b11111 sets maximum brightness. The SMBus interface does not control whether the device regulates the current by analog dimming, DPWM dimming or both, this is done by MINDAC (see Multimode Pin Description section)
Shutdown Mode Register [SHMD2-SHMD0] (POR = 0b001)
The 3-bit shutdown mode register configures the operation of the device when SH/SUS pin is toggled as described in Table 8. The shutdown mode register can also be used to directly shut off the CCFL regardless of the state of SH/SUS (Table 9).
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Table 8. SHMD Register Bit Descriptions
BIT NAME POR STATE 0 DESCRIPTION SHMD2 = 1 forces the lamp off and sets STATUS1. SHMD2 = 0 allows the lamp to operate although it may still be shutdown by the SH/SUS pin (depending on the state of SHMD1 and SHMD0). When SH/SUS = 0, this bit has no effect. SH/SUS = 1 and SHMD1 = 1 forces the lamp off and sets STATUS1. SH/SUS = 1 and SHMD1 = 0 allows the lamp to operate although it may still be shutdown by the SHMD2 bit. When SH/SUS = 1, this bit has no effect. SH/SUS = 0 and SHMD0 = 1 forces the lamp off and sets STATUS1. SH/SUS = 0 and SHMD0 = 0 allows the lamp to operate although it may still be shutdown by the SHMD2 bit.
2
SHMD2
1
SHMD1
0
0
SHMD0
1
Table 9. SH/SUS and SHMD Register Truth Table
SH/SUS 0 0 1 1 X SHMD2 0 0 0 0 1 SHMD1 X X 0 1 X SHMD0 0 1 X X X OPERATING MODE Operate Shutdown, STATUS1 set Operate Shutdown, STATUS1 set Shutdown, STATUS1 set
X = Don't care.
Table 10. Status Register Bit Descriptions (Read Only/Writes Have No Effect)
BIT NAME POR STATE 1 DESCRIPTION STATUS1 = 0 means that a lamp-out condition has been detected. The STATUS1 bit stays clear even after the lamp-out condition has gone away. The only way to set STATUS1 is to shut off the lamp by programming the mode register or by toggling SHB/SUS. STATUS0 = 0 means that an overcurrent condition was detected during the previous digital PWM period. STATUS0 = 1 means that no overcurrent condition was detected during the previous digital PWM period.
1
STATUS1
0
STATUS0
1
ID Registers
The ID registers return information on the manufacturer, the chip ID, and the chip revision number. The MAX1895 is the first-generation advanced CCFL controller and its ChipRev is 0x00. Reading from MfgID register returns 0x4D, which is the ASCII code for "M" (for Maxim), the ChipID register returns 0x96. Writing to these registers has no effect. TRANSISTOR COUNT: 7364
Chip Information
26
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High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
Pin Configurations (continued)
TOP VIEW
MAX1895/MAX1995
BATT
CCV
N.C.
VCC
CCI
28
27
26
25
24
23
22
VFB
IFB
ILIM REF MINDAC GND MODE CRF CTL
1 2 3 4 5 6 7 10 11 12 13 14 8 9
21 20 19
GH2 LX2 BST2 BST1 LX1 GH1 GL1
MAX1995
18 17 16 15
N.C.
N.C.
PGND
N.C.
THIN QFN
______________________________________________________________________________________
GL2
SH
VDD
27
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32L QFN.EPS 28 ______________________________________________________________________________________
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1895/MAX1995
______________________________________________________________________________________
29
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers MAX1895/MAX1995
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
1 2
30
______________________________________________________________________________________
QFN THIN 5x5x0.8 .EPS
High-Efficiency, Wide Brightness Range, CCFL Backlight Controllers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1895/MAX1995
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
PROPRIETARY INFORMATION
9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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